ARM is an architecture designed for building CPUs. ARM stands for Advanced RISC Machines. It provides the foundation for designing a processor, also known as the processing element.
There are three kinds of ARM architectures: A-profile for applications, R-profile for real-time systems, and M-profile for microcontrollers.
The below diagram displays ARM processor family:
An example of an ARM based system containing:
- A-profile processor with Android OS
- R-profile processor providing connectivity
- An M-profile based SecurCore processor for SIM card with security features
- M-profile processors for system power management.
System Architecture
The Arm architecture specifies: Instruction set, Register set, Exception model, memory model and Debug, trace and profiling.
The Arm architecture is the first layer providing a programmer’s model to software through Instruction Set Architecture(ISA) compatibility. Base System Architecture (BSA) specification describes the hardware system architecture that an OS needs. Server Base System Architecture(SBSA) describes hardware and feature requirements for a server OS. The Base Boot Requirement(BBR) specification establishes the firmware interface requirements (eg interface for PSCI, SMBIOS, ACPI, UEFI, etc).
Micro-architecture
The micro-architecture of a processor describes its build and design, outlining how the processor works.
Other ARM architectures
ARM has similar specifications for many of the components for making SoC. One example:
Common Architecture terms:
- Processing Element (PE): generic term for implementation of Arm architecture.
- IMPLEMENTATION DEFINED(IMP DEF): A feature which is IMP DEF is defined by a specific micro-architecture.
- UNPREDICTABLE and CONSTRAINED UNPREDICTABLE: These terms are used to describe things that software should not do.
- Deprecated: Before removing a feature completely, mark it as Deprecated.
- RES0 and RES1: RES0 means Reserved should be zero, RES1 means Reserved should be One.
CPU, memory, and RISC architecture
Arm processors use RISC (Reduced Instruction Set Computing) architecture. The CPU and memory use load/store architectures to fetch instructions from the instruction memory via the instruction bus and to load or store data into the data memory using the data bus. CPU contains General Purpose Registers (GPRs) and Special registers. GPRs are used for temporary data and results. Special registers are used for specific purposes like program counter, status register, configuration register, control register, interrupt mask register, etc.
To understand the CPU, we need to learn the programmer’s model, memory model, Exception model and Debug model. These models provide a comprehensive framework for how the CPU functions, handles memory, manages exception and supports debugging.
Programmer’s model describes the CPU registers, instruction sets, addressing modes, and operational features. It provides the foundation for how instructions are executed and how data is manipulated. It is essential for writing low-level code and understanding CPU capabilities.
Memory model describes the layout of memory, memory addressing, behaviour of caches and memory barriers. It helps in ensuring data consistency, optimising memory access and cache coherency.
Exception model outlines how the CPU handles the interrupts, traps and other exceptions. It describes the priority and processing of different types of exceptions, context switching mechanisms and state saving and restoring processes.
Debugging model defines the features and mechanisms available for debugging and tracing the execution of programs. It includes hardware breakpoints, watchpoints, debug registers and support for external debug interfaces.
Registers set
Below diagram shows ARM Cortex M registers info:
GPR R13 is used for stack pointer, R14 is used as link register that holds the return address for function calls or the address to return to after an exception or interrupt is handled. R15 is used as program counter(PC) that holds the address of the next instruction to be fetched and executed.
Special register xPSR is an execution program status register combination of EPSR, APSR and IPSR. It contains various flags and status bits related to current execution state of the CPU. Special register PRIMASK is a 1 bit register that controls masking of exceptions with configurable priority levels. Special registers CONTROL registers used for controlling and configuring of CPU operation, system behaviour and resource management.
Modes and Privileges
The following diagram shows the modes and privileges of Cortex-M series processors:
In ARM Cortex-M processors, the CPU can operate in thread mode or handler mode. Usually, the CPU runs in thread mode, and when an exception occurs, it switches to handler mode. In Cortex-M processors, privileged and non-privileged modes represent two execution states with different levels of access to system resources and privileged instructions. Privileged mode allows full access to system resources and is typically used by the operating system kernel and exception handlers, while non-privileged mode restricts access to certain resources and is used for user-level application code. In thread mode, CPU can be privileged or non-privileged, while in handler mode, it is always privileged. When the CPU boots, it starts in privileged thread mode. If the CONTROL register is configured with non-privileged mode, the CPU switches to non-privileged thread mode. Through software exceptions, the CPU can switch to privileged handler mode and privileged thread mode. From privileged handler mode, CPU can either switch to privileged thread mode or non-privileged thread mode.
MSP and PSP
In Cortex-M processors, main stack pointer(MSP) and process stack pointer (PSP) are used for managing stack memory. MSP points to system stack or exception stack used for storing the execution context during exceptions/interrupts. PSP points to the process stack or thread stack used for storing execution context in non-privileged thread mode. When CPU is in privileged thread mode or privileged handler mode, it uses MSP else it uses PSP.
