SPI (Serial Peripheral Interface) Controller allows SPI transfers. MTS is Master transaction split option allows SPI transfers to be broken into smaller segments. When this option is enabled, SPI controller splits the single SPI transaction into multiple small sub-transactions, these are processed in sequence.
When MTS is set to 1 the transaction is a split transfer whereby the TX-FIFO contents are transmitted, then SPI Data I/O lines reverse and the byte number according to the TX-RX-FBCR register are read from the external SPI slave and written into the RX-FIFO. To use this option other SWD (SPI Write Disable) and SRD (SPI Read Disable) options should be set to 1.
It is used along with MTE (Master Transfer Enable) set to 1. Setting MTE initiates the SPI control to conduct a SPI master transfer. MTE set by CPU indicating SPI master configured and data transferred should be initiated. To know a Master transfer completed, MTC in interrupt register ISR sets.
TX-RX-FBCR (TX-RX-Fifo Byte Count Register) is used by Master-Receive when Master Transmitter inactive. That is in half duplex mode, when SPI master RX-FIFO receives burst without TX-FIFO filled by CPU and sending data on MO output. TX-RX-FBCR is set with the number of bytes the SPI master-receive should read from the external SPI slave. It is 8 bits for 256 byte FIFO implementation.
